In an MOS static random access memory (SRAM), a data bit of a memory cell is typically read and written by a signal represented as a differential voltage between two bit lines. Multiple memory cells are coupled to one bit line pair and form a column of the memory, with each memory cell located on one row of the column. Each memory cell has a unique address at an intersection of a row and a column. The bit line pairs are commonly used for both reading data from and writing data to the memory cell. Using the differential bit line pairs in such a way creates certain problems. Consider the case of a by-one (.times.1) memory. A .times.1 memory is organized to read or store one bit per address; similarly, a .times.8 memory is organized to read or store eight bits per address. In the .times.1 memory, when a write cycle begins, a data bit is provided to the memory and an address selects one memory cell to which the data bit is to be written. The data bit is received into the memory and driven onto a pair of write global data lines, which extend form one end of the memory to another end and, through further decoding, onto a selected bit line pair. The data bit is driven onto the bit line pair as a differential voltage between the two bit lines. The differential voltage is large enough to overwrite an existing value in the selected memory cell. Typically the differential voltage on the bit lines is approximately 3 volts. When a read cycle takes place, a selected memory cell provides a data bit stored within the selected memory cell as a differential voltage on the bit line pair. The differential voltage for the read cycle is approximately 300 millivolts.
A problem arises when a write cycle is completed and a read cycle begins. The differential voltage remaining on the bit line pair at the end of the write cycle must be reduced to a level low enough so that the data is not erroneously written into a memory cell during the ensuing read cycle. The differential voltage on the bit line pair must also be reduced quickly so that the read cycle is not unnecessarily extended. This process is called equalization. Equalization may include either coupling a first bit line of a bit line pair to a second bit line of the bit line pair so that their voltages will approach each other or coupling both lines to a reference voltage, commonly a 5 volt power supply voltage terminal V.sub.DD, or both. However achieved, equalization must make the voltages on the first and second bit lines of the bit line pair close enough so that data is not overwritten and that the correct data is sensed quickly during the read cycle. The requirement of the equalization circuitry to quickly equalize the voltages on the bit line pairs is embodied in a timing specification known as TWHAX, or the time from a write signal high, or inactive, to an address invalid, signifying a change in address as a start of the read cycle. SRAMs require increasingly fast read access times, and correspondingly, improved values for TWHAX.
Equalization is typically achieved by placing a circuit known as a bit line load on each of the bit line pairs. At the termination of the write cycle the bit line loads either couple the first bit line to the second bit line of the bit line pairs, or couple each bit line to a power supply voltage terminal such as V.sub.DD, or both. Because of the speed required, capacitive loading on the bit lines is not insignificant, and a rise time caused by such capacitance and a resistance of the bit lines limit the speed at which the bit lines equalize. As memory sizes increase capacitance increases, since capacitance is proportional to the conductor area. Another problem with a typical way of performing equalization by bit line loads is caused by decreasing geometries of memory cells. Columns with multiple memory cells coupled to them are placed adjacent to each other. In order for the bit line load not to increase column width, the bit line loads must fit within the width of the memory cells in the column. This requirement restricts the size of transistors in the bit line loads, which causes the equalization to proceed more slowly and worsens TWHAX.
An apparatus for equalizing the bit lines via the global data lines is taught by Abe et al in U.S. Pat. No. 4,110,840, entitled "Sense Line Charging System for Random Access Memory". The global data lines used by Abe et al. are tied to multiple bit line pairs and are used to sense data during the read cycle. However, as memory sizes have increased, this approach has become less valuable, because the length of the global data lines has increased the amount of capacitance on the bit line pairs during a read cycle, which considerably slows equalization performed by such a load.